The Level Sensitive Scan Design (LSSD), as fully disclosed in U.S. Pat. No. 3,783,254 and patent application Ser. No. 701,052, require that the sequential logic network be controlled by two or more non-overlapping clock signals. Thus, in a system designed within these constraints for testability, there must exist a network that generates two or more non-overlapping clock pulses. In the past, this clock generation network has not conformed to the LSSD rules and hence, had to be physically isolated from the LSSD portion of the system. The clock generation network of the prior art suffered from lack of testability.
The clock generation network disclosed herein not only generates at least two non-overlapping clock signals but also conforms to the LSSD design rules. Consequently, it has the following advantages over other clock generation networks. Namely, (1) the network is fully testable. (2) The network can be integrated on the same chip containing the LSSD design. This saves on chip I/O and improves performance. (3) The LSSD test generation system will generate tests for the clock network as well as for the LSSD network.
(Reference is made to U.S. Pat. Nos. 3,761,697, 3,783,254 and 3,784,907, respectively granted to E. B Eichelberger and of common assignee herewith.)